////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: P.40xd
//  \   \         Application: netgen
//  /   /         Filename: fulladd_timesim.v
// /___/   /\     Timestamp: Tue Jan 29 13:01:26 2013
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -sdf_anno true -sdf_path netgen/fit -insert_glbl true -w -dir netgen/fit -ofmt verilog -sim fulladd.nga fulladd_timesim.v 
// Device	: XA9536XL-15-VQ44 (Speed File: Version 3.1)
// Input file	: fulladd.nga
// Output file	: E:\ise\14.3\mywork\fulladd\netgen\fit\fulladd_timesim.v
// # of Modules	: 1
// Design Name	: fulladd.nga
// Xilinx        : E:\ise\14.3\ISE_DS\ISE\
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module fulladd (
  a, b, c_in, c_out, sum
);
  input a;
  input b;
  input c_in;
  output c_out;
  output sum;
  wire a_IBUF_1;
  wire b_IBUF_3;
  wire c_in_IBUF_5;
  wire c_out_OBUF_7;
  wire sum_OBUF_9;
  wire \c_out_OBUF.Q_10 ;
  wire \c_out_OBUF.D_11 ;
  wire \c_out_OBUF.D1_12 ;
  wire \c_out_OBUF.D2_13 ;
  wire \c_out_OBUF.D2_PT_0_14 ;
  wire \c_out_OBUF.D2_PT_1_15 ;
  wire \c_out_OBUF.D2_PT_2_16 ;
  wire \sum_OBUF.Q_17 ;
  wire \sum_OBUF.D_18 ;
  wire \sum_OBUF.D1_19 ;
  wire \sum_OBUF.D2_20 ;
  wire \sum_OBUF.D2_PT_0_21 ;
  wire \sum_OBUF.D2_PT_1_22 ;
  wire \NlwBufferSignal_c_out_OBUF.D/IN0 ;
  wire \NlwBufferSignal_c_out_OBUF.D/IN1 ;
  wire \NlwBufferSignal_c_out_OBUF.D2_PT_0/IN0 ;
  wire \NlwBufferSignal_c_out_OBUF.D2_PT_0/IN1 ;
  wire \NlwBufferSignal_c_out_OBUF.D2_PT_1/IN0 ;
  wire \NlwBufferSignal_c_out_OBUF.D2_PT_1/IN1 ;
  wire \NlwBufferSignal_c_out_OBUF.D2_PT_2/IN0 ;
  wire \NlwBufferSignal_c_out_OBUF.D2_PT_2/IN1 ;
  wire \NlwBufferSignal_c_out_OBUF.D2/IN0 ;
  wire \NlwBufferSignal_c_out_OBUF.D2/IN1 ;
  wire \NlwBufferSignal_c_out_OBUF.D2/IN2 ;
  wire \NlwBufferSignal_sum_OBUF.D/IN0 ;
  wire \NlwBufferSignal_sum_OBUF.D/IN1 ;
  wire \NlwBufferSignal_sum_OBUF.D1/IN0 ;
  wire \NlwBufferSignal_sum_OBUF.D1/IN1 ;
  wire \NlwBufferSignal_sum_OBUF.D2_PT_0/IN0 ;
  wire \NlwBufferSignal_sum_OBUF.D2_PT_0/IN1 ;
  wire \NlwBufferSignal_sum_OBUF.D2_PT_1/IN0 ;
  wire \NlwBufferSignal_sum_OBUF.D2_PT_1/IN1 ;
  wire \NlwBufferSignal_sum_OBUF.D2/IN0 ;
  wire \NlwBufferSignal_sum_OBUF.D2/IN1 ;
  wire \NlwInverterSignal_sum_OBUF.D/IN0 ;
  wire \NlwInverterSignal_sum_OBUF.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_sum_OBUF.D2_PT_1/IN1 ;
  initial $sdf_annotate("netgen/fit/fulladd_timesim.sdf");
  X_IPAD   \a.PAD  (
    .PAD(a)
  );
  X_BUF   a_IBUF (
    .I(a),
    .O(a_IBUF_1)
  );
  X_IPAD   \b.PAD  (
    .PAD(b)
  );
  X_BUF   b_IBUF (
    .I(b),
    .O(b_IBUF_3)
  );
  X_IPAD   \c_in.PAD  (
    .PAD(c_in)
  );
  X_BUF   c_in_IBUF (
    .I(c_in),
    .O(c_in_IBUF_5)
  );
  X_OPAD   \c_out.PAD  (
    .PAD(c_out)
  );
  X_BUF   c_out_8 (
    .I(c_out_OBUF_7),
    .O(c_out)
  );
  X_OPAD   \sum.PAD  (
    .PAD(sum)
  );
  X_BUF   sum_10 (
    .I(sum_OBUF_9),
    .O(sum)
  );
  X_BUF   c_out_OBUF (
    .I(\c_out_OBUF.Q_10 ),
    .O(c_out_OBUF_7)
  );
  X_BUF   \c_out_OBUF.Q  (
    .I(\c_out_OBUF.D_11 ),
    .O(\c_out_OBUF.Q_10 )
  );
  X_XOR2   \c_out_OBUF.D  (
    .I0(\NlwBufferSignal_c_out_OBUF.D/IN0 ),
    .I1(\NlwBufferSignal_c_out_OBUF.D/IN1 ),
    .O(\c_out_OBUF.D_11 )
  );
  X_ZERO   \c_out_OBUF.D1  (
    .O(\c_out_OBUF.D1_12 )
  );
  X_AND2   \c_out_OBUF.D2_PT_0  (
    .I0(\NlwBufferSignal_c_out_OBUF.D2_PT_0/IN0 ),
    .I1(\NlwBufferSignal_c_out_OBUF.D2_PT_0/IN1 ),
    .O(\c_out_OBUF.D2_PT_0_14 )
  );
  X_AND2   \c_out_OBUF.D2_PT_1  (
    .I0(\NlwBufferSignal_c_out_OBUF.D2_PT_1/IN0 ),
    .I1(\NlwBufferSignal_c_out_OBUF.D2_PT_1/IN1 ),
    .O(\c_out_OBUF.D2_PT_1_15 )
  );
  X_AND2   \c_out_OBUF.D2_PT_2  (
    .I0(\NlwBufferSignal_c_out_OBUF.D2_PT_2/IN0 ),
    .I1(\NlwBufferSignal_c_out_OBUF.D2_PT_2/IN1 ),
    .O(\c_out_OBUF.D2_PT_2_16 )
  );
  X_OR3   \c_out_OBUF.D2  (
    .I0(\NlwBufferSignal_c_out_OBUF.D2/IN0 ),
    .I1(\NlwBufferSignal_c_out_OBUF.D2/IN1 ),
    .I2(\NlwBufferSignal_c_out_OBUF.D2/IN2 ),
    .O(\c_out_OBUF.D2_13 )
  );
  X_BUF   sum_OBUF (
    .I(\sum_OBUF.Q_17 ),
    .O(sum_OBUF_9)
  );
  X_BUF   \sum_OBUF.Q  (
    .I(\sum_OBUF.D_18 ),
    .O(\sum_OBUF.Q_17 )
  );
  X_XOR2   \sum_OBUF.D  (
    .I0(\NlwInverterSignal_sum_OBUF.D/IN0 ),
    .I1(\NlwBufferSignal_sum_OBUF.D/IN1 ),
    .O(\sum_OBUF.D_18 )
  );
  X_AND2   \sum_OBUF.D1  (
    .I0(\NlwBufferSignal_sum_OBUF.D1/IN0 ),
    .I1(\NlwBufferSignal_sum_OBUF.D1/IN1 ),
    .O(\sum_OBUF.D1_19 )
  );
  X_AND2   \sum_OBUF.D2_PT_0  (
    .I0(\NlwBufferSignal_sum_OBUF.D2_PT_0/IN0 ),
    .I1(\NlwBufferSignal_sum_OBUF.D2_PT_0/IN1 ),
    .O(\sum_OBUF.D2_PT_0_21 )
  );
  X_AND2   \sum_OBUF.D2_PT_1  (
    .I0(\NlwInverterSignal_sum_OBUF.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_sum_OBUF.D2_PT_1/IN1 ),
    .O(\sum_OBUF.D2_PT_1_22 )
  );
  X_OR2   \sum_OBUF.D2  (
    .I0(\NlwBufferSignal_sum_OBUF.D2/IN0 ),
    .I1(\NlwBufferSignal_sum_OBUF.D2/IN1 ),
    .O(\sum_OBUF.D2_20 )
  );
  X_BUF   \NlwBufferBlock_c_out_OBUF.D/IN0  (
    .I(\c_out_OBUF.D1_12 ),
    .O(\NlwBufferSignal_c_out_OBUF.D/IN0 )
  );
  X_BUF   \NlwBufferBlock_c_out_OBUF.D/IN1  (
    .I(\c_out_OBUF.D2_13 ),
    .O(\NlwBufferSignal_c_out_OBUF.D/IN1 )
  );
  X_BUF   \NlwBufferBlock_c_out_OBUF.D2_PT_0/IN0  (
    .I(a_IBUF_1),
    .O(\NlwBufferSignal_c_out_OBUF.D2_PT_0/IN0 )
  );
  X_BUF   \NlwBufferBlock_c_out_OBUF.D2_PT_0/IN1  (
    .I(b_IBUF_3),
    .O(\NlwBufferSignal_c_out_OBUF.D2_PT_0/IN1 )
  );
  X_BUF   \NlwBufferBlock_c_out_OBUF.D2_PT_1/IN0  (
    .I(a_IBUF_1),
    .O(\NlwBufferSignal_c_out_OBUF.D2_PT_1/IN0 )
  );
  X_BUF   \NlwBufferBlock_c_out_OBUF.D2_PT_1/IN1  (
    .I(c_in_IBUF_5),
    .O(\NlwBufferSignal_c_out_OBUF.D2_PT_1/IN1 )
  );
  X_BUF   \NlwBufferBlock_c_out_OBUF.D2_PT_2/IN0  (
    .I(b_IBUF_3),
    .O(\NlwBufferSignal_c_out_OBUF.D2_PT_2/IN0 )
  );
  X_BUF   \NlwBufferBlock_c_out_OBUF.D2_PT_2/IN1  (
    .I(c_in_IBUF_5),
    .O(\NlwBufferSignal_c_out_OBUF.D2_PT_2/IN1 )
  );
  X_BUF   \NlwBufferBlock_c_out_OBUF.D2/IN0  (
    .I(\c_out_OBUF.D2_PT_0_14 ),
    .O(\NlwBufferSignal_c_out_OBUF.D2/IN0 )
  );
  X_BUF   \NlwBufferBlock_c_out_OBUF.D2/IN1  (
    .I(\c_out_OBUF.D2_PT_1_15 ),
    .O(\NlwBufferSignal_c_out_OBUF.D2/IN1 )
  );
  X_BUF   \NlwBufferBlock_c_out_OBUF.D2/IN2  (
    .I(\c_out_OBUF.D2_PT_2_16 ),
    .O(\NlwBufferSignal_c_out_OBUF.D2/IN2 )
  );
  X_BUF   \NlwBufferBlock_sum_OBUF.D/IN0  (
    .I(\sum_OBUF.D1_19 ),
    .O(\NlwBufferSignal_sum_OBUF.D/IN0 )
  );
  X_BUF   \NlwBufferBlock_sum_OBUF.D/IN1  (
    .I(\sum_OBUF.D2_20 ),
    .O(\NlwBufferSignal_sum_OBUF.D/IN1 )
  );
  X_BUF   \NlwBufferBlock_sum_OBUF.D1/IN0  (
    .I(a_IBUF_1),
    .O(\NlwBufferSignal_sum_OBUF.D1/IN0 )
  );
  X_BUF   \NlwBufferBlock_sum_OBUF.D1/IN1  (
    .I(a_IBUF_1),
    .O(\NlwBufferSignal_sum_OBUF.D1/IN1 )
  );
  X_BUF   \NlwBufferBlock_sum_OBUF.D2_PT_0/IN0  (
    .I(b_IBUF_3),
    .O(\NlwBufferSignal_sum_OBUF.D2_PT_0/IN0 )
  );
  X_BUF   \NlwBufferBlock_sum_OBUF.D2_PT_0/IN1  (
    .I(c_in_IBUF_5),
    .O(\NlwBufferSignal_sum_OBUF.D2_PT_0/IN1 )
  );
  X_BUF   \NlwBufferBlock_sum_OBUF.D2_PT_1/IN0  (
    .I(b_IBUF_3),
    .O(\NlwBufferSignal_sum_OBUF.D2_PT_1/IN0 )
  );
  X_BUF   \NlwBufferBlock_sum_OBUF.D2_PT_1/IN1  (
    .I(c_in_IBUF_5),
    .O(\NlwBufferSignal_sum_OBUF.D2_PT_1/IN1 )
  );
  X_BUF   \NlwBufferBlock_sum_OBUF.D2/IN0  (
    .I(\sum_OBUF.D2_PT_0_21 ),
    .O(\NlwBufferSignal_sum_OBUF.D2/IN0 )
  );
  X_BUF   \NlwBufferBlock_sum_OBUF.D2/IN1  (
    .I(\sum_OBUF.D2_PT_1_22 ),
    .O(\NlwBufferSignal_sum_OBUF.D2/IN1 )
  );
  X_INV   \NlwInverterBlock_sum_OBUF.D/IN0  (
    .I(\NlwBufferSignal_sum_OBUF.D/IN0 ),
    .O(\NlwInverterSignal_sum_OBUF.D/IN0 )
  );
  X_INV   \NlwInverterBlock_sum_OBUF.D2_PT_1/IN0  (
    .I(\NlwBufferSignal_sum_OBUF.D2_PT_1/IN0 ),
    .O(\NlwInverterSignal_sum_OBUF.D2_PT_1/IN0 )
  );
  X_INV   \NlwInverterBlock_sum_OBUF.D2_PT_1/IN1  (
    .I(\NlwBufferSignal_sum_OBUF.D2_PT_1/IN1 ),
    .O(\NlwInverterSignal_sum_OBUF.D2_PT_1/IN1 )
  );
endmodule


`ifndef GLBL
`define GLBL

`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule

`endif

